A class of non-volatile memory devices known as "flash" EEPROMs (electrically erasable programmable read only memory devices), combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature which distinguishes flash EEPROMs from standard EEPROMs is that unlike standard EEPROMs, flash EEPROMs do not contain a select transistor on a one-for-one basis with each floating gate transistor. A select transistor provides for the selection of an individual memory cell within the memory device and can be used to selectively erase a specific memory cell. Because flash EEPROMs do not contain a select transistor on a one-for-one basis with each floating gate transistor, flash EEPROM memory cells are erased in bulk, either by erasing the entire chip or by erasing paged groups of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.
Typically, a plurality of flash EEPROM cells are formed on a single semiconductor substrate (i.e. a silicon die). FIG. 1 illustrates a single conventional flash EEPROM memory cell. As depicted in FIG. 1, flash memory cell 100 is formed on a P-type substrate 110 and includes an N-type double-diffused source region 102 and a N+ drain region 104. A substrate electrode 126 is attached to substrate 110. Drain region 104 and source region 102 are spaced apart from each other with channel region 122 interposed there between. Source electrode 114 and drain electrode 112 are respectively connected to source region 102 and drain region 104.
The double-diffused source region 102 is formed of a lightly doped N region 128 (phosphorous doped) and a more heavily doped but shallower N+ region 130 (arsenic doped), embedded within the deep N region 128. The phosphorous contained within N region 128 grades the source junction and thus reduces the horizontal electric (E.sub.H) field 134 between the source region 102 and the substrate 110 in the pn junction.
The floating gate 106 is insulatively disposed a short distance above at least one of the source and/or drain regions by a dielectric layer 118. Above the floating gate 106 and insulatively disposed in the dielectric layer 116, is a control gate 108. A control gate electrode 120 is attached to control gate 108. L.sub.GATE 132 represents the gate length for the gates contained in flash memory cell 100.
In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing "hot electron" injections from a portion of the substrate (i.e., usually a channel section near the drain region), into the floating gate. The injected electrons carry a negative charge into the floating gate and are typically induced by grounding the source region of the substrate, biasing the control gate to a relatively high positive voltage to create an electron tracking field and biasing the drain region to a positive voltage of moderate magnitude in order to generate hot (high energy) electrons.
For example, to program flash memory cell 100, source electrode 114 is tied to ground, drain electrode 112 is tied to a relatively high voltage (e.g. +4 volts to +9 volts) and the control gate electrode 120 is connected to a relatively high voltage level (e.g., +8 volts to +12 volts). Electrons are accelerated from source region 102 to drain region 104 and so-called "hot electrons" are generated near the drain region 104. Some of the hot electrons are injected through the relatively thin gate dielectric layer 118 and become trapped in the floating gate 106 thereby giving floating gate 106 a negative potential.
After sufficient negative charge accumulates on floating gate 106, the negative potential of floating gate 106 raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel 122 during a subsequent "read" mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.
Conversely, to erase a flash memory device, electrons are typically driven out of the floating gate 106 by biasing the control gate 108 to a large negative voltage and the source region 102 to a low positive voltage, in order to produce a sufficiently large vertical electric field (E.sub.V) in the tunnel oxide. This effect happens because the floating gate 106 reaches a large negative voltage through a capacitive coupling with the control gate 108. The sufficiently large vertical electric field (E.sub.V 136) in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate 106 through the tunnel oxide and into the source region 102. The charge taken from the floating gate 106 in turn produces a threshold voltage shift (V.sub.T shift) which can be used to deprogram (erase) the device.
For example, during erasure a relatively low positive voltage (i.e. +0.5 V to +5.0 V) is applied to source electrode 114 and a relatively large negative voltage (i.e. -7 V to -13 V) is applied to control gate electrode 120. The voltage of substrate electrode 126 is grounded (0 V) and drain electrode 112 is allowed to float. The vertical electric field (E.sub.V 136) established between the control gate 108 and the source region 102 induces electrons previously stored in floating gate 106 to pass through dielectric layer 118 and into source region 102 by way of Fowler-Nordheim tunneling.
In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate 108 to a large enough negative voltage such that the floating gate 106 reaches a voltage of approximately -5.5 volts. A typical potential difference V.sub.SF between the source region 102 and floating gate 106 is on the order of 10 volts and accordingly, when the source voltage V.sub.S is made less positive, the control gate voltage V.sub.CG should be made more negative. Once the source to floating voltage V.sub.SF is selected, the remaining factors are preferably constrained according to the equation: EQU V.sub.FG =.alpha..sub.CG (V.sub.CG -.DELTA.V.sub.T)+.alpha..sub.S V.sub.S +.alpha..sub.B V.sub.B
where: PA1 where:
V.sub.FG =the floating gate voltage; PA2 V.sub.CG =the control gate voltage; PA2 V.sub.S =the source voltage; PA2 V.sub.B =the substrate or p-well bias; PA2 .DELTA.V.sub.T =the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate; PA2 .alpha..sub.CG =the capacitive coupling coefficient from the control gate to the floating gate; PA2 .alpha..sub.S =the capacitive coupling coefficient between the source and the floating gate; PA2 .alpha..sub.B =the capacitive coupling coefficient between the substrate or p-well and the floating gate. PA2 J.sub.b-t-b =band-to-band current density [A/cm.sup.2 ] PA2 A.sub.b-t-b,B.sub.b-t-b =constants PA2 .function.(E) sometimes modeled as E.sup.2 PA2 E=SQRT (E.sub.V.sup.2 +E.sub.H.sup.2) (the tunneling field in the junction).
As technology advances, a continuing goal throughout the industry is to increase the density of memory devices. By reducing the size of a flash EEPROM device a greater memory capacity can be achieved. In using more dies per wafer the cost per die can reduced. In addition, using higher density memory devices may provide for a reduction in the over all power consumption.
In order to increase the memory density of flash EEPROM devices, the memory cells are typically scaled down in size (e.g. reduction in overall footprint of the device) by reducing the gate length (L.sub.GATE 132) and gate width (W.sub.GATE 138). However, a problem with reducing the length of the memory cell gates is that the distance between the source region 102 and the drain region 104 is also reduced. As the source region 102 approaches the drain region 104 the lateral diffusion from the phosphorous in the source region (N region 128) causes a leakage between the source region 102 and the drain region 104 resulting in detrimental short channel effects. Short channel effects produce serious problems in the flash memory cells and are typically evident when the gate length (L.sub.GATE 132) is reduced below 0.4 microns.
One method for reducing the short-channel effect is by eliminating the N double-diffused phosphorous region. By using a single-diffused source region, the phosphorous diffusion overlap distance L.sub.DD 124 is no longer present and the short channel effect problem is significantly reduced. Eliminating the phosphorous diffusion overlap distance L.sub.DD 124 allows for a gate length (L.sub.GATE 132) reduction below 0.4 microns and therefore provides for an increased packing density of the memory cells.
However, eliminating the phosphorous doped N region 128 produces an unwanted side-effect of increasing the horizontal electric (E.sub.H) field 134 between the source region 102 and the substrate 110 in the pn junction during erasure of the memory cell. This increase in the horizontal electric (E.sub.H) field 134 directly contributes to an increase in the band-to-band current since it is generally accepted that: EQU J.sub.b-t-b =A.sub.b-t-b .function.(E)e.sup.-(B.sub.b-t-b.sup./E)
Because of the source-to-substrate biasing during the erasure of the memory cell device, a reversed-biased pn junction is formed which produces band-to-band currents (also known as Zener currents) in the source junction. The band-to-band currents are normally several orders of magnitude larger than the Fowler-Nordheim current. This band-to-band current is hard to sustain from a circuit design point of view and is also believed to generate detrimental reliability problems such as hole trapping in the tunnel oxide.
Hole trapping can potentially affect the floating gate's ability to retain a negative charge (electrons), as the trapped holes have a tendency to migrate to the floating gate 106 and to neutralize the negative charge therein. The production of holes at the surface of the dielectric 118 below the floating gate 106 is undesirable as it can interfere with reliable programming, reading and erasure of randomly located memory cells, known as the gate disturb phenomenon. This gate disturb phenomenon occurs because holes trapped in the tunnel oxide layer tend to migrate upwardly into the floating gate 106 to neutralize negative program charges and thus decrease the charge retention time of the floating gate 106.
More specifically, during erasure some memory cells may produce more hot holes than others and, consequently, some floating gates will be discharged faster than others. This creates a non-uniform erasure throughout the memory chip. Holes that do not migrate to the floating gate 106 during erasure can remain in the dielectric 118 for random periods of time. These holes can later migrate into the floating gate 106 after the memory cell has been programmed and neutralize part of the programming charge that is to be retained.
In addition to the detrimental hole trapping, the band-to-band currents require additional current from the memory chip charge pumps. Because the movement in the industry has generally been to reduce the supply voltage for memory chips, the charge pump efficiency has also been reduced and therefore cannot support the band-to-band currents. Under this condition, the source bias is decreased thus reducing the cell erase speed.
Therefore, it is highly desirable to devise a method for reducing band-to-band currents in flash memory cells while still providing for gate size reduction without inducing detrimental short channel effects.